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february 2012 doc id 17811 rev 2 1/17 17 srk2000 synchronous rectifier smart driver for llc resonant converters features secondary-side synchronous rectifier controller optimized for llc resonant converters protection against current reversal safe management of load transient, light load and startup condition intelligent automatic sleep-mode at light load dual gate driver for n-channel mosfets with 1 a source and 3.5 a sink drive current operating voltage range 4.5 to 32 v programmable uvlo with hysteresis 250 a quiescent consumption operating frequency up to 500 khz so8 package applications all-in-one pc high-power ac-dc adapters 80+/85+ compliant atx smps 90+/92+ compliant server smps industrial smps description the srk2000 smart driver implements a control scheme specific to secondary-side synchronous rectification in llc resonant converters that use a transformer with center-tap secondary winding for full-wave rectification. it provides two high-current gate-drive outputs, each capable of driving one or more n-channel power mosfets. each gate driver is controlled separately and an interlocking logic circuit prevents the two synchronous rectifier mosfets from conducting simultaneously. the control scheme in this ic allows for each synchronous rectifier to be switched on as the corresponding half-winding starts conducting and switched off as its current goes to zero. a unique feature of this ic is its intelligent automatic sleep- mode. it allows the detection of a low-power operating condition for the converter and puts the ic into a low consumption sleep-mode where gate driving is stopped and quiescent consumption is reduced. in this way, converter efficiency improves at light load, where synchronous rectification is no longer beneficial. the ic automatically exits sleep-mode and restarts switching as it recognizes that the load for the converter has increased. a noticeable feature is the very low external component count required. figure 1. internal block diagram table 1. device summary order code package packing srk2000d so-8 tube SRK2000DTR tape and reel so-8 '$ 0'.$ $2)6%2 '$ 6## 6 56,/ 6 56,/ $63 $63 3'.$ 6 #/.42/, ,/')# $2)6%2 4)-%23 6 2egulator %. /6%24%-0 3%.3/2 6 #522%.46/,4!'% #/-0!2!4/23 www.st.com
contents srk2000 2/17 doc id 17811 rev 2 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 en pin: pin function and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.1 pull-up resistor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.2 resistor divider configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.3 remote on/off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 drain voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 intelligent automatic sleep-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 protection against current reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
srk2000 pin description doc id 17811 rev 2 3/17 1 pin description figure 2. pin configuration table 2. pin description n. name function 1sgnd signal ground. return of the bias current of the device and 0 v reference for drain-to-source voltage monitors of both sections. route this pin directly to pgnd. 2en drain voltage threshold setting for synchronous rectifier mosfet turn-off. uvlo threshold programming. this pin is typically biased by either a pull-up resistor connected to vcc or by a resistor divider sensing vcc. pulling the pin to ground disables the gate driver outputs gd1 and gd2 and can therefore be used also as enable input. 3 4 dvs1 dvs2 drain voltage sensing for sections 1 and 2. these pins are to be connected to the respective drain terminals of the corresponding synchronous rectifier mosfet via limiting resistors. when the voltage on either pin goes negative, the corresponding synchronous rectifier mosfet is switched on; as its (negative) voltage exceeds a threshold defined by the en pin, the mosfet is switched off. an internal logic rejects switching noise, however, extreme care in the proper routing of the drain connection is recommended. 5 7 gd2 gd1 gate driver output for sections 2 and 1. each totem pole output stage is able to drive power mosfets with a peak current of 1 a source and 3.5 a sink. the high-level voltage of these pins is clamped at about 12 v to avoid excessive gate voltages in case the device is supplied with a high vcc. 6pgnd power ground. return for gate-drive currents. route this pin to the common point where the source terminals of both synchronous rectifier mosfets are connected. 8vcc supply voltage of the device. a small bypass capacitor (0.1 f typ.) to sgnd, located as close to the ic?s pins as possible, may be useful to obtain a clean supply voltage for the internal control circuitry. a similar bypass capacitor to pgnd, again located as close to the ic?s pins as possible, may be an effective energy buffer for the pulsed gate-drive currents. gd2 sgnd en dvs1 dvs2 vcc gd1 pgnd 1 2 3 4 8 7 6 5 gd2 sgnd en dvs1 dvs2 vcc gd1 pgnd 1 2 3 4 8 7 6 5
pin description srk2000 4/17 doc id 17811 rev 2 figure 3. typical system block diagram ,! 3)&35(5(*8/$725237,21$/ //&5(621$17+$/)%5,'*(:,7+6<1&+5(&7 65 32+ rxwgf 9 rxwgf 9 lqdf 9 lqdf 9 ,! ,3(
srk2000 maximum ratings doc id 17811 rev 2 5/17 2 maximum ratings 3 typical application schematic figure 4. typical application schematic table 3. absolute maximum ratings symbol pin parameter value unit vcc 8 dc supply voltage -0.3 to vcc z v icc z 8 internal zener maximum current 25 ma --- 2, 3, 4 analog inputs voltage rating -0.3 to vcc z v i dvs1,2_sk 3, 4 analog inputs max. sink current (single pin) 25 ma i dvs1,2_sr 3, 4 analog inputs max. source current (single pin) -5 ma table 4. thermal data symbol parameter value unit r thja max. thermal resistance, junction-to-ambient 150 c/w ptot power dissipation @ t a = 50 c 0.65 w t j junction temperature operating range -40 to 150 c t stg storage temperature -55 to 150 c rxwgf 9 9lq 65 //& / rxwgf 9 rxwgf 9 rxwgf 9 rxwgf 9 9lq 9lq 65. /$
electrical characteristics srk2000 6/17 doc id 17811 rev 2 4 electrical characteristics t j = -25 to 125 c, v cc = 12 v, c gd1 = c gd2 = 4.7 nf, en = v cc ; unless otherwise specified; typical values refer to t j = 25 c. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit supply voltage v cc operating range after turn-on 4.5 32 v v ccon turn-on threshold (1) 4.25 4.5 4.75 v v ccoff turn-off threshold (1) 4 4.25 4.5 v hys hysteresis 0.25 v vcc z zener voltage icc z = 20 ma 33 36 39 v supply current i start-up startup current before turn-on, vcc = 4 v 45 70 a iq quiescent current after turn-on 250 500 a i cc operating supply current @ 300 khz 35 ma iq quiescent current en = sgnd 150 250 a drain sensing inputs and synch functions v dvs1,2_h upper clamp voltage i dvs1,2 = 20 ma vcc z v i dvs1,2_b input bias current v dvs1,2 = 0 to vcc (2) -1 1 a v dvs1,2_a arming voltage (positive-going edge) 1.4 v v dvs1,2_pt pre-triggering voltage (negative-going edge) 0.7 v v dvs1,2_th turn-on threshold -250 -200 -180 i dvs1,2_on turn-on source current v dvs1,2 = -250 mv -50 a v dvs1,2_off turn-off threshold (positive-going edge) r = 680 k ? from en to vcc -18 -25 -32 mv r = 270 k ? from en to vcc -9 -12.5 -16 t pd_on turn-on debounce delay after sourcing i ds1,2_on 250 ns t pd_off turn-off propagation delay after crossing v ds1,2_off 60 ns t on_min minimum on-time 150 ns d off min. operating duty-cycle 40 % d on restart duty-cycle 60 % gate-drive enable function v en_on enable threshold positive-going edge (1) 1.7 1.8 1.9 v hyst hysteresis below v en_on 45 mv
srk2000 electrical characteristics doc id 17811 rev 2 7/17 symbol parameter test condition min. typ. max. unit i en bias current v en = v en_on 1a turn-off threshold selection v en-th selection threshold v cc = v ccon 0.32 0.36 0.40 v i en pull-down current v en = v en_th , v cc = v ccon 71013a gate drivers v gdh output high voltage i gdsource = 5 ma 11.75 11.9 v i gdsource = 5 ma, vcc = 5 v 4.75 4.9 v gdl output low voltage i gdsink = 200 ma 0.2 v i gdsink = 200 ma, vcc = 5 v 0.2 i sourcepk output source peak current -1 a i sinkpk output sink peak current 3.5 a t f fall time 18 ns t r rise time 40 ns v gdclamp output clamp voltage i gdsource = 5 ma; vcc = 20 v 12 13 15 v v gdl_uvlo uvlo saturation vcc = 0 to v ccon isink = 5 ma 11.3v 1. parameters tracking each other. 2. for vcc>30 v i dvs1,2_b may be greater than 1 a because of the possible current contribution of the internal clamp zener (few tens of a). table 5. electrical characteristics (continued)
application information srk2000 8/17 doc id 17811 rev 2 5 application information 5.1 en pin: pin function and usage this pin can perform three different functions: it sets the threshold v dvs1,2_off for the drain- to-source voltage of either synchronous rectifier (sr) power mosfet to determine their turn-off in each conduction cycle; it allows the user to program the uvlo thresholds of the gate drivers and can be used as enable (remote on/off control). 5.1.1 pull-up resistor configuration at startup, an internal 10 a current sink (i en ) is active as long as the device supply voltage vcc is below the startup threshold v ccon . the moment vcc equals v ccon (4.5 v typ.), the voltage v en on the en pin determines the turn-off threshold v dvs1,2_off for the drain voltage of both synchronous rectifiers during their cycle-by-cycle operation: if v en < v en_th (= 0.36 v) the threshold is set at -25 mv, otherwise at -12 mv. once the decision is made, the setting is frozen as long as vcc is greater than the turn-off level v ccoff (4.25 v typ.). a simple pull-up resistor r 1 to vcc can be used to set v dvs1,2_off turn-off threshold. the voltage on the en pin as the device turns on is given by: then, considering worst-case scenarios, we have: some additional margin (equal to the resistor's tolerance) needs to be considered; assuming 5% tolerance, the use of the standard values r 1 = 680 k ? in the first case and r 1 = 270 k ? in the second case, is suggested. figure 5. en pin biased with a pull-up resistor (for logic-level mosfet driving) as vcc exceeds v ccon , the internal current sink i en is switched off and the enable function is activated. the voltage on the pin is then compared to an internal reference v en_on set at 1 r i v v en ccon en ? = mv 25 v k 633 1 r off _ 2 , 1 dvs ? = ? > mv 12 v k 296 1 r off _ 2 , 1 dvs ? = ? <
srk2000 application information doc id 17811 rev 2 9/17 1.8 v: if this threshold is exceeded the gate drivers gd1 and gd2 are enabled and the sr mosfet is operated; otherwise, the device stays in an idle condition and the sr mosfet in the off state. using the pull-up resistor r p , the voltage on the en pin rises as i en is switched off and tends to vcc, therefore exceeding v en_on and enabling the operation of both sr mosfets. essentially, this results in enabling the gate-driving as vcc exceeds v ccon and disabling it as vcc falls below v ccon . this configuration is thereby recommended when sr mosfets are logic-level types. 5.1.2 resistor divider configuration to enable gate-driving with a vcc voltage higher than a predefined value v cc_g , to properly drive a standard sr mosfet, the en pin is biased by a resistor divider (r1 upper resistor, r2 lower resistor) whose value is chosen so as to exceed v en_on when vcc = v cc_g and also to set the desired v dvs1,2_off level. note that, with a falling vcc, gate-driving is disabled at a vcc level about 2.5% lower than v cc_g , because of the 45 mv hysteresis of the comparator. the equations that describe the circuit in the two crucial conditions vcc = v ccon (when the decision of the v dvs1,2_off level is made) and vcc = v cc_g (when gate-driving is to be enabled) are respectively: figure 6. en pin biased with a resistor divider to program the gate-drive uvlo threshold v cc_g equation 1 solving these equations for r 1 and r 2 we get: ? ? ? ? ? = + + = ? on _ en g _ cc en en en ccon v 2 r 1 r 2 r v 2 r v i 1 r v v
application information srk2000 10/17 doc id 17811 rev 2 equation 2 if v cc_g is not too low (<89 v), its tolerance is not critical because it is related only to that of v en_on (5.6%) and of the external resistors r1, r2 (1% each is recommended). then, some care needs to be taken only as far as the selection of the -12/-25 mv threshold is concerned: in fact, the large spread of i en considerably affects the voltage on the en pin as the device turns on, a value that can be found by solving the first of (1) for v en : equation 3 a couple of examples clarify the suggested calculation methodology. example 1 v cc_g = 10 v, v dvs1,2_off = - 25 mv. in this case, v en must definitely be lower than the minimum value of v en_th (= 0.32 v). from the second of (2), the nominal ratio of r1 to r2 is (10 ? 1.8) / 1.8 = 4.555. substituting the appropriate extreme values in (3) it must be (4.75 - 710 -6 r1) / (1 + 4.555) < 0.32; solving for r1 yields r1 > 425 k ? ; let us consider an additional 4% margin to take both the tolerance and the granularity of the r1 and r2 values into account, so that: r1 > 4251.04 = 442 k ? . choose r1 = 442 k ? (e48 standard value) and, from the second of (2), r2 = 442/4.555 = 97 k ? ; use 97.6 k ? (e48 standard value). example 2 v cc_g = 10 v, v dvs1,2_off = - 12 mv. in this case, v en must definitely be higher than the maximum value of v en_th (= 0.40 v). from the second of (2), the nominal ratio of r1 to r2 is (10 ? 1.8) / 1.8 = 4.555. substituting the appropriate extreme values in (3) it must be (4.25 - 1310 -6 r1) / (1 + 4.555) > 0.4; solving for r1 yields r1 < 156 k ? ; with 4% additional margin r1 < 156/1.04 = 150 k ? . choose r1 = 147 k ? (e48 standard value) and, from the second of (2), r2 = 147/4.555 = 32.3 k ? ; use 32.4 k ? (e48 standard value). note: in both examples the gate drivers are disabled as vcc falls below 9.75 v (nominal value), as the voltage on the en pin falls 45 mv below v en_on . ? ? ? ? ? ? ? ? ? ? = ? = on _ en g _ cc on _ en en on _ en g _ cc en ccon v v v 1 r 2 r i v v v v 1 r 2 r 1 r 1 1 r i v v en ccon en + ? =
srk2000 application information doc id 17811 rev 2 11/17 5.1.3 remote on/off control whichever configuration is used, since a voltage on the en pin 45 mv below v en_on disables the gate drivers, any small-signal transistor can be used to pull down the en pin and force the gate drivers into an off state. finally, it should be noted that during power-up, power-down, and under overload or short- circuit conditions, the gate drivers are shut down if the vcc voltage is insufficient: < v ccoff in case of pull-up resistor configuration, < 0.975 tv cc_g in case of resistor divider configuration (the coefficient 0.975 depends on the hysteresis on the enable pin threshold). 5.2 drain voltage sensing in the following explanations it is assumed that the reader is familiar with the llc resonant half bridge topology and its waveforms, especially those on the secondary side with a center-tap transformer winding for full-wave rectification. to understand the polarity and the level of the current flowing in the sr mosfets (or their body diodes, or diodes in parallel to the mosfets) the ic is provided with two pins, dvs1- 2, able to sense the voltage level of the mosfet drains. figure 7. typical waveform seen on the drain voltage sensing pins the logic that controls the driving of the two sr mosfets is based on two gate-driver state machines working in parallel in an interlocked way to avoid both gate drivers being switched on at the same time. there are four significant drain voltage thresholds: the first one, v dvs1,2_a (= 1.4 v), sensitive to positive-going edges, arms the opposite gate driver (interlock function); the second, v dvs1,2_pt (=0.7 v), sensitive to negative-going edges, provides a pre-trigger of the gate driver; the third is the (negative) threshold v th-on that triggers the gate driver as the body diode of the sr mosfet starts conducting; the fourth is the internal (negative) threshold v dvs1,2_off where the sr mosfet is switched off (selectable between -12 mv or -25 mv by properly biasing the en pin). the value of the on threshold v th-on is affected by the external resistor in series to each dvs1-2 pin needed essentially to limit the current that might be injected into the pins when one sr mosfet is off and the other sr mosfet is conducting. in fact, on the one hand, when one mosfet is off (and the other one is conducting), its drain-to-source voltage is
application information srk2000 12/17 doc id 17811 rev 2 slightly higher than twice the output voltage; if this exceeds the voltage rating of the internal clamp (vcc z = 36 v typ.), a series resistor r d must limit the injected current below an appropriate value, lower than the maximum rating (25 ma) and taking the related power dissipation into account. on the other hand, when current starts flowing into the body diode of one mosfet (or in the diode in parallel with the mosfet), the drain-to-source voltage is negative ( ? -0.7 v); when the voltage on pins dvs1,2 reaches the threshold v dvs1,2_th (- 0.2v typ.), an internal current source i dvs1,2_on is activated; as this current exceeds 50 a, the gate of the mosfet is turned on. therefore, the actual triggering threshold can be determined by the following formula: for instance, with r d = 2 k ? , the triggering threshold is located at - (2 k ? ? 50 a) - 0.2 v = -0.3 v. to avoid false triggering of the gate driver, a debounce delay t pd_on (= 250 ns) is used after sourcing i ds1,2_on (i.e. the current sourced by the pin must exceed 50 a for more than 250 ns before the gate driver is turned on). this delay is not critical for the converter?s efficiency because the initial current is close to zero or anyway much lower than the peak value. once the sr mosfet has been switched on, its drain-to-source voltage drops to a value given by the flowing current times the mosfet r ds(on) . again, since the initial current is low, the voltage drop across the r ds(on) may exceed the turn-off threshold v dvs1,2_off , and determine an improper turn-off. to prevent this, the state machine enables the turn-off comparator referenced to v dvs1,2_off only in the second half of the conduction cycle, based on the information of the duration of the previous cycle. in the first half of the conduction cycle only an additional comparator, referenced to zero, is active to prevent the current of the sr mosfet from reversing, which would impair the operation of the llc converter. once the threshold v dvs1,2_off is crossed (in the second half of the conduction cycle) and the gate is turned off, the current again flows through the body diode causing the drain-to- source voltage to have a negative jump, going again below v th-on . the interlock logic, however, prevents a false turn-on. it is worth pointing out that, due to the fact that each mosfet is turned on after its body diode starts conducting, the on transition happens with the drain-source voltage equal to the body diode forward drop; therefore there is neither a miller effect nor switching losses at mosfet turn-on. also at turn-off the switching losses are not present, in fact, the current is always flowing from source to drain and, when the mosfet is switched off, it goes on flowing through the body diode (or the external diode in parallel to the mosfet). unlike at turn-on, the turn-off speed is critical to avoid current reversal on the secondary side, especially when the converter operates above the resonance frequency, where the current flowing through the mosfet exhibits a very steep edge while decreasing down to zero: the turn-off propagation t pd_off delay has a maximum value of 60 ns. the interlock logic, in addition to checking for consistent secondary voltage waveforms (one mosfet can be turned on only if the other one has a positive drain-to-source voltage > v dvs1,2_a ) to prevent simultaneous conduction, allows only one switching per cycle: after one gate driver has been turned off, it cannot be turned on again before the other gate drive has had its own on/off cycle. the ic logic also prevents unbalanced current in the two sr mosfets: if one sr mosfet fails to turn on in one cycle, the other sr mosfet is also not turned on in the next cycle. th _ 2 , 1 dvs on 2 , 1 dvs d on th v i r v + ? = ?
srk2000 application information doc id 17811 rev 2 13/17 figure 8. typical connection of the srk2000 to the sr mosfet 5.3 gate driving the ic is provided with two high-current gate-drive outputs (1 a source and 3.5 a sink), each capable of driving one or more n-channel power mosfets. thanks to the programmable gate-drive uvlo, it is possible to drive both standard mosfets and logic level mosfets. the high-level voltage provided by the driver is clamped at v gdclamp (=12 v) to avoid excessive voltage levels on the gate in case the device is supplied with a high vcc. the two gate drivers have a pull-down capability that ensures the sr mosfets cannot be spuriously turned on even at low vcc: in fact, the drivers have a 1 v (typ.) uvlo saturation level at vcc below the turn-on threshold. 5.4 intelligent automatic sleep-mode a unique feature of this ic is its intelligent automatic sleep-mode. the logic circuitry is able to detect a light load condition for the converter and stop gate driving, also reducing the ic?s quiescent consumption. this improves converter efficiency at light load, where the power losses on the rectification body diodes (or external diodes in parallel to the mosfets) go lower than the power losses in the mosfets and those related to their driving. the ic is also able to detect an increase of the converter?s load and automatically restart gate driving. the algorithm used by the intelligent automatic sleep-mode is based on a dual time measurement system. the duration of a switching cycle of an sr mosfet (that is one half of the resonant converter switching period) is measured using a combination of the negative-going edge of the drain-to-source voltage falling below v dvs1,2_pt and the positive-going edge exceeding v dvs1,2_a ; the duration of the sr mosfet conduction is measured from the moment its body diode starts conducting (drain-to-source voltage falling below v th-on ) to the moment the gate drive is turned off (in case the device is operating) or the moment the body diode ceases to conduct (drain-to-source voltage going over v th-on ). while at full load the sr mosfet conduction time occupies almost 100% of the switching cycle, as the load is reduced, the conduction time is reduced and as it falls below 40% (d off ) of the sr mosfet switching cycle the device enters sleep-mode. to prevent srk2000 gd1 to xfo rmer dvs1 sr1 i sr1 r d r g srk2000 gd1 to xfo rmer dvs1 sr1 i sr1 r d r g
application information srk2000 14/17 doc id 17811 rev 2 erroneous decisions, the sleep-mode condition must be confirmed for 16 consecutive switching cycles of the resonant converter (i.e. 16 consecutive cycles for each sr mosfet of the center-tap). once in sleep-mode, sr mosfet gate driving is re-enabled when the conduction time of the body diode (or the external diodes in parallel to the mosfet) exceeds 60% (d on ) of the switching cycles. also in this case the decision is made considering the measurement on 8 consecutive switching cycles (i.e. 8 consecutive cycles for each sr mosfet of the center- tap). furthermore, after each sleep-mode entering/exiting transition, the timing is ignored for a certain number of cycles, to let the resulting transient in the output current fade out; then the time check is enabled. the number of ignored resonant converter switching cycles is 128 after entering sleep-mode and 256 after exiting sleep-mode. 5.5 protection against current reversal the ic provides protection against sr mosfet current reversal. if a current reversal condition is detected for two consecutive switching cycles, the ic goes into sleep-mode, avoiding the turn-on of the sr mosfets until a safe condition is restored. 5.6 layout guidelines the ic is designed with two grounds, sgnd and pgnd. sgnd is used as the ground reference for all the internal high-precision analog blocks, while pgnd is the ground reference for all the noisy digital blocks, as well as the current return for the gate drivers. in addition, it is also the ground for the esd protection circuits. sgnd is protected by esd events versus pgnd through two anti-parallel diodes. when laying out the pcb, make sure to keep the source terminals of both sr mosfets as close as possible to one another and to route the trace that goes to pgnd separately from the load current return path. this trace should be as short as possible and be as close to the physical source terminals as possible. a layout that is as geometrically symmetrical as possible helps the circuit to operate in the most electrically symmetrical way as possible. sgnd should be directly connected to pgnd using a path as short as possible (under the device body). also drain voltage sensing should be performed as physically close to the drain terminals as possible: any stray inductance crossed by the load current that is in the drain-to-source voltage sensing circuit may significantly alter the current reading, leading to a premature turn-off of the sr mosfet. it is worth mentioning that, especially in higher power applications or at higher operating frequencies, even the stray inductance of the internal wire bonding can be detrimental. in this case, a cautious selection of the sr mosfet package is required. the use of bypass capacitors between vcc and both sgnd and pgnd is recommended. they should be low-esr, low-esl types and located as close to the ic pins as possible. sometimes a series resistor (in the tens) between the converter's output voltage and the vcc pin, forming an rc filter along with the bypass capacitor, is useful in order to get a cleaner vcc voltage.
srk2000 package mechanical data doc id 17811 rev 2 15/17 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 1. so-8 mechanical data dim. mm. inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. d dimensions do not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs should not exceed 0.15 mm (.006 inch) in total (both sides). 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 9. package dimensions
revision history srk2000 16/17 doc id 17811 rev 2 7 revision history table 6. document revision history date revision changes 10-aug-2010 1 initial release. 08-feb-2012 2 minor text changes to improve readability in features, on cover page, and chapter 5 . added chapter 5.5: protection against current reversal . document status promoted from preliminary data to datasheet.
srk2000 doc id 17811 rev 2 17/17 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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